This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-024887, filed Jan. 31, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a software/hardware language model conversion method and computer program product for automatically converting a software description into a hardware operation description.
2. Description of the Related Art
Recently, attention has been given to the design of an overall system or hardware by using a software description language such as C, C++, or specification description language SpecC (described in detail in xe2x80x9cSpecC: Specification Language and Methodologyxe2x80x9d, Daniel D. Gajski, Kluwer Academic Publishers, Dordrecht, ISBN0-7923-7822-9). This is a technique of describing a specification in a software description language and converting it into a specification in a hardware description language such as VHDL or Verilog to connect it to a downstream logic synthesizing tool in proceeding to detailed design of hardware.
Some tools for creating a hardware language model in the C language have already been commercialized. However, the codes to be input to such a tool are limited to those describing sequential processing. The tool is useful for partial design, but is not suitable for large-scale design because it includes portions that cannot be satisfactorily written in the form of a sequential specification. Demands have therefore arisen for software/hardware language model conversion that can support parallel programs.
Assume that a description in a software description language includes parallel programs. In this case, when the language is converted into a hardware description language at operation level, the manner of handling shared variables cannot be directly converted. More specifically, in software, values are determined in accordance with the order in which assignment is executed. In hardware description, if signal outputs from the respective parallel programs are simply connected, the values become undefined or determined regardless of the assignment order. Demands have therefore arisen for a method of systematically converting assignment to shared variables into assignment in hardware description.
Assume that a description in a software description language includes procedure calls that can operate parallel. In this case, when this description is converted into a hardware description language at operation level, the manner of handling calls for the same procedure cannot be directly converted. More specifically, if parallel procedures are replaced with processes, identical procedures can be simultaneously called. If, however, this operation is directly expressed by shake-hands using signals between the processes, exclusive calling cannot be realized. Demands have therefore arisen for a method of systematically creating an exclusive calling mechanism in the form of a code.
The present invention has been made in consideration of the above situation, and has as its object to provide a software/hardware language model conversion method and computer program product for converting a software description including parallel programs and variables shared among them into a hardware description at operation level which operates in the same manner as the software description.
It is another object to provide a software/hardware language model conversion method and computer program product for realizing exclusive process execution processing corresponding to procedure calling in converting parallel programs in a software language into a hardware description.
According to one aspect of the present invention, there is provided a software/hardware language model conversion method for converting a first code described in a software description language to a second code described in a hardware description language. The method comprises: converting the first code to the second code; detecting a plurality of processes from the second code, the processes corresponding to a plurality of parallel procedures in the first code, which assign values to a predetermined shared variable; and generating a value solving process for the detected processes corresponding to the parallel procedures, wherein the value solving process includes pairs of a data signal and an assignment timing signal from each of the detected processes as an input, and includes any one of data signals corresponding to a change of the assignment timing signal, as an output.